Analysis of Transistor Networks Generation

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of previous methods. We describe which figures of merit, including the logical effort, affect the design quality of a cell transistor network. Further, we propose and compare two different approaches that generate transistor network with guaranteed theoretical minimum length transistor chains, showing it reduces significantly the logical effort of the networks.